This patent relates to techniques for reducing the number of programmable circuit elements that are programmed to implement a user design, and more particularly, to techniques for combining functional blocks into fewer programmable circuit elements.
Programmable logic devices (such as Altera's Stratix family of products) typically include rows and columns of programmable circuit elements. Programmable circuit elements are blocks of circuitry that are coupled together through routing resources such as interconnection conductors. A programmable circuit element may, for example, contain registers, a look-up table, memory circuits, multiplexers and/or other circuits. Programmable circuit elements can be programmed to perform a variety of user functions. An example of a programmable circuit element is a logic element, which usually contains a look-up table and a register and some support circuitry for arithmetic and other functions.
A programmable logic device (PLD) can be configured according to a user design by programming the logic elements, the routing resources, and any other programmable circuit elements. Often when a PLD is configured, functional blocks in the user design are programmed into more logic elements in the PLD than necessary.
For example, a user design may include functional blocks that are performed by a look-up table and a register. In the user design, the output of the look-up table is coupled to an input of the register. A look-up table coupled to an input of a register is referred to as a normal template.
When the PLD is configured, a first logic element is programmed to perform the function of the look-up table, and a second logic element coupled to the first logic element is programmed to perform the function of the register. Because each logic element includes a register and a look-up table, the register and the look-up function in the user design can be combined into one logic element in the PLD. This would reduce the number of logic elements in the PLD that are needed to configure the PLD according to the user design.
One exemplary prior art algorithm searched through user designs and identified normal templates that were programmed into more than one logic element. The algorithm then combined the register and the look-up table functions into one logic element to increase the density of the circuit design. However, this prior art algorithm did not take into consideration how timing delays in the user design would be effected by combining functional blocks.
It would therefore be desirable to provide techniques for combining functional blocks into fewer programmable circuit elements that takes into consideration changes in timing delays caused by these combinations.